Rebuilding a design system across five internal products
Rebuilding a design system across five internal products
I built the components for two new internal apps, starting with the resume reviewer’s candidate table, then helped audit and rebuild the shared design system so five products could stay consistent.
Role
Product designer (contract)
Timeline
April 2025 to January 2026
Team
Head of design, two senior designers, two product designers
Skills
Languages: C++, Python, Go, Java
Tools: Git, Docker, Kubernetes, AWS, Bazel
Frameworks: Spring, React, Node.js, gRPC
Experience Areas: Distributed systems, Low-latency systems, Market data processing
Education
- ACM ICPC Regional Finalist, 2017
- Teaching Assistant, Advanced Algorithms
Experience
- Designed and shipped a core service processing real-time market data at over 2M messages per second, reducing p99 latency by 40%.
- Led a cross-team initiative to migrate legacy infrastructure to a distributed microservice architecture.
- Mentored three incoming engineers and led onboarding for the team’s internal tooling.
- Filed one internal patent for a caching optimization technique adopted across two product areas.
- Built and maintained backend services for a real-time inventory platform used by 200+ retail partners.
- Improved deployment pipeline reliability, reducing failed releases by 25%.
- Built a real-time telemetry pipeline processing sensor data from autonomous test vehicles.
- Presented findings to senior engineering leadership; recommendations were adopted into the production roadmap.
Projects
- Open-source contributor to a columnar storage engine: vectorized two aggregation paths.
- Wrote a deterministic simulator for testing consensus protocols under network partitions.
Skills
Languages: C++, Rust, Python, OCaml
Tools: Git, Bazel, Linux perf, Terraform
Frameworks: gRPC, Arrow, Kafka, Flink
Experience Areas: Exchange connectivity, Matching engines, Performance engineering
Education
- Thesis: lock-free queues for multi-core order routing
- Head Tutor, Operating Systems
Experience
- Rebuilt an order gateway in Rust, cutting median round-trip latency by 38%.
- Owned capacity planning and failover drills for a system handling 4M orders a day.
- Introduced continuous latency benchmarking, catching three regressions before release.
- Led a team of four through a regulator-driven audit of order handling.
- Maintained market data feed handlers for six exchanges, with zero missed sessions over three years.
- Cut cold-start time of the pricing service from 90 to 12 seconds.
- Designed a binary wire format that halved bandwidth between co-located sites.
- Mentored five new graduates through their first production releases.
- Wrote a time-series compression library adopted by two internal research teams.
- Built tooling to replay production traffic against staging builds.
- Moved nightly batch jobs to a streaming pipeline, cutting report delay from hours to minutes.
- Profiled a packet-capture service and removed a lock that capped throughput at 40%.
- Wrote the fuzz tests that now gate every release of the parser.
Projects
- Maintainer of a small Rust crate for lock-free ring buffers.
- Speaker at a regional systems meetup on tail latency in order routing.
- Author of an open-source latency histogram viewer used in two university courses.
Patents
- "Lock-Free Queue for Multi-Core Order Routing," filed 2021. Sole inventor; in production in the Halden & Pryce order gateway.
Awards
- Engineering Excellence Award, Halden & Pryce, 2022.
- Graduate Prize for Best Thesis in Computer Engineering, Wexmoor University, 2014.
- ID
- 15203362
- Source
- Sourcing Campaign
- Tech Score
- 94.6
- Years of Experience
- 6
- AI Summary
- This candidate combines strong academic credentials with high-impact engineering work at scale: leading a latency-critical migration and shipping a patented optimization within the first two years on the job signals both technical depth and unusual trust from senior stakeholders early in a career.
- ID
- 20846137
- Source
- Employee Referral
- Tech Score
- 93.5
- Years of Experience
- 10
- AI Summary
- A performance specialist with a decade in exchange-facing systems. The order gateway rebuild shows end-to-end ownership, from design through capacity planning, and the teaching record suggests someone who raises the level of the engineers around them.
Lines of Code: 35K C++ / 20K Python / 15K Go / 8K Java
Google Scholar: Unavailable
GitHub: Link
- "Method and System for Adaptive Cache Optimization in Distributed Services," filed 2023.
Lines of Code: 60K C++ / 25K Rust / 10K Python / 4K OCaml
Google Scholar: Unavailable
GitHub: Link
- "Lock-Free Queue for Multi-Core Order Routing," filed 2021.
At a glance
Over ten months I built components for two new internal apps for a quantitative investment firm. Building both showed the shared design system had drifted across five products. I helped audit the system and rebuild the shared components with better documentation.
Problem
We were brought in to build two new internal apps: one for screening hundreds of candidates a day and one for performance reviews for 3,000+ employees. As we worked on the interfaces, the existing design system was used inconsistently across products. With many teams working at the same time, components had drifted and upkeep had fallen behind. Different products were creating their own patterns. I noticed this most while building tables, states, and shared components. The products needed more customization than the system allowed.
An internal resume reviewer to assess large pools of candidates.
An internal resume reviewer to assess large pools of candidates.
The senior designers designed the reviewer. My part was the candidate table: making sure every state and variant was captured, built into the design system as a component, and consistent with it.
Skills
Languages: C++, Python, Go, Java
Tools: Git, Docker, Kubernetes, AWS, Bazel
Frameworks: Spring, React, Node.js, gRPC
Experience Areas: Distributed systems, Low-latency systems, Market data processing
Education
- ACM ICPC Regional Finalist, 2017
- Teaching Assistant, Advanced Algorithms
Experience
- Designed and shipped a core service processing real-time market data at over 2M messages per second, reducing p99 latency by 40%.
- Led a cross-team initiative to migrate legacy infrastructure to a distributed microservice architecture.
- Mentored three incoming engineers and led onboarding for the team’s internal tooling.
- Filed one internal patent for a caching optimization technique adopted across two product areas.
- Built and maintained backend services for a real-time inventory platform used by 200+ retail partners.
- Improved deployment pipeline reliability, reducing failed releases by 25%.
- Built a real-time telemetry pipeline processing sensor data from autonomous test vehicles.
- Presented findings to senior engineering leadership; recommendations were adopted into the production roadmap.
Projects
- Open-source contributor to a columnar storage engine: vectorized two aggregation paths.
- Wrote a deterministic simulator for testing consensus protocols under network partitions.
Skills
Languages: C++, Rust, Python, OCaml
Tools: Git, Bazel, Linux perf, Terraform
Frameworks: gRPC, Arrow, Kafka, Flink
Experience Areas: Exchange connectivity, Matching engines, Performance engineering
Education
- Thesis: lock-free queues for multi-core order routing
- Head Tutor, Operating Systems
Experience
- Rebuilt an order gateway in Rust, cutting median round-trip latency by 38%.
- Owned capacity planning and failover drills for a system handling 4M orders a day.
- Introduced continuous latency benchmarking, catching three regressions before release.
- Led a team of four through a regulator-driven audit of order handling.
- Maintained market data feed handlers for six exchanges, with zero missed sessions over three years.
- Cut cold-start time of the pricing service from 90 to 12 seconds.
- Designed a binary wire format that halved bandwidth between co-located sites.
- Mentored five new graduates through their first production releases.
- Wrote a time-series compression library adopted by two internal research teams.
- Built tooling to replay production traffic against staging builds.
- Moved nightly batch jobs to a streaming pipeline, cutting report delay from hours to minutes.
- Profiled a packet-capture service and removed a lock that capped throughput at 40%.
- Wrote the fuzz tests that now gate every release of the parser.
Projects
- Maintainer of a small Rust crate for lock-free ring buffers.
- Speaker at a regional systems meetup on tail latency in order routing.
- Author of an open-source latency histogram viewer used in two university courses.
Patents
- "Lock-Free Queue for Multi-Core Order Routing," filed 2021. Sole inventor; in production in the Halden & Pryce order gateway.
Awards
- Engineering Excellence Award, Halden & Pryce, 2022.
- Graduate Prize for Best Thesis in Computer Engineering, Wexmoor University, 2014.
- ID
- 15203362
- Source
- Sourcing Campaign
- Tech Score
- 94.6
- Years of Experience
- 6
- AI Summary
- This candidate combines strong academic credentials with high-impact engineering work at scale: leading a latency-critical migration and shipping a patented optimization within the first two years on the job signals both technical depth and unusual trust from senior stakeholders early in a career.
- ID
- 20846137
- Source
- Employee Referral
- Tech Score
- 93.5
- Years of Experience
- 10
- AI Summary
- A performance specialist with a decade in exchange-facing systems. The order gateway rebuild shows end-to-end ownership, from design through capacity planning, and the teaching record suggests someone who raises the level of the engineers around them.
Lines of Code: 35K C++ / 20K Python / 15K Go / 8K Java
Google Scholar: Unavailable
GitHub: Link
- "Method and System for Adaptive Cache Optimization in Distributed Services," filed 2023.
Lines of Code: 60K C++ / 25K Rust / 10K Python / 4K OCaml
Google Scholar: Unavailable
GitHub: Link
- "Lock-Free Queue for Multi-Core Order Routing," filed 2021.
A new performance review system to support over 3,000 employees.
A new performance review system to support over 3,000 employees.
The senior designers designed the components for Cadence, the performance review product. My part was making sure every variant was captured, added to the design system, and consistent with it.
Maya Ellison
2026 Year-End Self Review
Deliver the migration of the end-of-day risk reporting pipeline to the new scheduling platform ahead of the Q3 control review.
The migration completed three weeks ahead of the review with no missed or restated reports. I staged the cutover by desk so that each group could validate its own outputs against the legacy run before sign-off, and documented the reconciliation checks so they can be audited independently.
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Maya Ellison
2025 Year-End Self Review
Assume ownership of the monthly risk reporting pack from the outgoing lead.
I took ownership in March after a six-week handover. The pack had been assembled by hand from eleven sources, so my first step was to document each one and who relied on it. Automating the reconciliation step reduced preparation from four days to two, and every pack since has gone out on schedule with no restatements. I also added a short commentary page, which the desk heads now read first.
Establish working relationships with the three groups that depend on our data.
I set up a monthly review with each group and published a shared change calendar. Two of the three now raise schema changes with us before release, which has eliminated most of the late corrections we were absorbing. The third relationship is still more reactive than I would like; I have agreed a quarterly planning session with their lead to address that.
Reduce the number of manual interventions in the overnight batch.
Interventions fell from an average of nine a month to two. Most of the improvement came from fixing three recurring data-quality issues at source instead of patching them downstream. The remaining interventions are tied to a legacy scheduler, which is why I have proposed its replacement as a goal for next year.
The accomplishment I am most satisfied with is redesigning the reconciliation process, which was outside my original goals. It had been a known weak point for some time, and I was able to make the case for fixing it by quantifying the hours it cost each month. I then trained two colleagues to run it so that it no longer depends on me. Separately, I covered the team lead’s responsibilities during the autumn planning round, which gave me a first experience of setting priorities across the group rather than within my own work.
I would particularly value feedback in two areas. The first is how I present trade-offs to senior stakeholders: I suspect I give too much detail before the recommendation, and I would like to know whether that is how it lands. The second is how effectively I delegate under deadline pressure, since my instinct in those moments is still to take the work back.
First, I stay too close to delivery detail once a deadline is at risk. I need to set clearer checkpoints up front so that I can step back without losing sight of quality. Second, I am slower than I should be to raise a concern when it involves another group’s work; agreeing escalation routes at the start of a project would make that easier. Third, I have not yet invested enough in understanding the trading context behind the reports we produce, and plan to spend time with two desks next year to close that gap.
My main project goal is to lead the migration of the risk reporting pipeline to the new scheduling platform, with the cutover complete ahead of the Q3 control review. My development goal is to bring the two analysts joining the team to the point where each owns a workstream independently, which will also test whether I can delegate properly. I would additionally like to take part in one cross-group planning cycle from start to finish.
I am grateful for the latitude I was given to redesign the reconciliation process, and for the time my manager spent helping me frame the case for it. I would welcome more exposure to the planning discussions that set our priorities, as I think I could contribute to them and it would help me explain the reasoning behind those priorities to the team.
Approach
I joined as one of two product designers on a contract team with a head of design and two senior designers. The senior designers led the direction for both apps. My part: • Built the resume reviewer’s candidate table, with every state and variant • Extended it to show custom statuses the standard data table didn’t support • Turned new pieces into reusable components for both apps As a team: • Checked both products against the existing system and flagged drift • Audited all five apps toward the end of the contract • Rebuilt the shared system from MUI, adding only what the audit found missing • Handed off a library ready to publish, documented in Confluence
Audit findings

All 60+ components we reviewed across the five products, compared against the shared system to find where they’d drifted.
Common patterns we found during the audit
Common patterns we found during the audit
Some components were being used incorrectly
In one product, chips were built from a modified button even though a chip component already existed.
Some components were being used incorrectly
In one product, chips were built from a modified button even though a chip component already existed.
Teams changed components without publishing back
Teams modified components and added new elements without updating the central system.
Navigation varied across products
Navigation varied across products
No shared pattern for side navigation, accordions, or cards. Each product created its own.
The system didn’t support needed behaviors
The system didn’t support needed behaviors
Some components lacked feedback states and couldn’t be edited without detaching. Overlays and draggable dividers had no system support.
Fixing the drift by rebuilding
Fixing the drift by rebuilding

The same chip built several different ways across products. One product used a modified button instead of the chip component.

Rebuilt so it could handle icons, avatars, and closable states without local overrides.
Outcome
By the end of the contract the firm had designs for the two new apps and a rebuilt design system. We audited all five products and rebuilt the shared components so they were more flexible and consistent across the suite. That meant people saw the same patterns in every product, with less to relearn and fewer chances to make mistakes. For each rebuilt component we wrote documentation in Confluence. I made a glossary that linked to every component. The products we helped ship still use the new design system. We also left them a way to keep it up so the patterns wouldn’t drift again. After I left, the hiring team used the system’s components to build and publish a new page for early graduates.
2
New internal apps
5
Internal products audited
1
Design system rebuilt and documented
Chip
Overview
A chip is a compact element that represents one discrete piece of information: an attribute, a filter, a person or a selection. Chips let people see and act on these values at a glance.
When to use
Use a chip for short, scannable values that belong to something else on the screen. Use another component when:
- The element starts an action. Use a Button.
- It takes people somewhere else. Use a Link or Tabs.
- People pick one option from a short set. Use a Radio group or Toggle button.
Types
| Type | What it does | Example |
|---|---|---|
| Input | Represents something a person added, such as a reviewer. Can be removed. | SLSam Lee |
| Filter | Shows a filter applied to a table or search. Removing it clears the filter. | Efficiency |
| Attribute | Labels a record with a category or status. Read-only. | Python |
Anatomy
Specs
The Chip comes in one size, sized for dense tables and forms.
| Property | Value |
|---|---|
| Height | 32px |
| Corner radius | 8px |
| Side padding | 8px |
| Label padding | 6px each side |
| Label | Open Sans SemiBold, 14/20 |
| Icon | 18px |
| Avatar | 24px |
Variants
Two styles, filled and outlined, each with optional elements, in four colors. Use filled for input and filter chips, and outlined for read-only attributes. Grey is the default; color adds meaning, so pair it with a clear label.
States
Focused applies when a chip is reached by keyboard and adds a focus ring. Disabled chips can’t be removed or selected.
Best practices
Do
- Keep labels to one or two words, so a row of chips scans quickly.
- Show chips close to the content they describe or filter.
- Let people undo removing a filter chip when it changes their results.
Don’t
- Don’t use a chip to start an action or to navigate.
- Don’t cut off a label without a way to read the full text.
- Don’t let a long list of chips push content down. Collapse extras into “+3 more”.
Accessibility
- Every chip that can be removed is reachable by keyboard, and Delete or Backspace removes it.
- The delete icon has an accessible name that includes the label, like “Remove Python”.
- Labels meet 4.5:1 contrast and icons meet 3:1 against every chip color.
- Status is never shown by color alone. Pair it with a label or an icon.
Reflection
The inconsistencies only became clear once we were building two products on the system at the same time. Next time I would audit the shared system before designing the first screens.
Reflection
The inconsistencies only became clear once we were building two products on the system at the same time. Next time I would audit the shared system before designing the first screens.

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